Vertical power DMOS (VDMOS) devices are currently used in the automotive industry to produce current smart power switches for applications such as automobile control circuits. In these applications, the most serious failure mode is destructive damage occurring during inductive switching, resulting from avalanche breakdown of the forward blocking junction in the presence of high current flow. A VDMOS device incorporates a semiconductor wafer in which source, body and drain regions of alternate conductivity type are disposed in series. The body region is disposed adjacent to a wafer surface, and the source and drain regions are located so as to define the length and width of a channel region in the body region at that surface. An insulated gate electrode is disposed on the wafer surface over the channel region.
During device operation, an appropriate voltage on the gate electrode inverts the conductivity type of the body region in that portion of the channel region that is contiguous with the wafer surface; so as to form an inversion channel contiguous with the wafer surface The remainder of the channel region comprises a depletion region which is associated with this inversion channel. For a particular device structure, the depth of the depletion region portion of the channel region is determined by the magnitude of the voltage applied to the gate electrode, and the inversion channel permits current flow between the source and drain regions. Thus, device operation is described as being unipolar in nature, with electron or hole flow being selectively modulated by an applied voltage to the gate.
Inherent in the source/body/drain structure of a VDMOS device is a parasitic NPN or PNP bipolar transistor the presence of which is detrimental to FET performance. With reference to FIGS. 1 to 6, there are illustrated devices 1 including a substrate 2 of a first conductivity type which constitutes or comprises the drain region 3 of high conductivity, an epitaxial layer 4 of n-polarity, a diffused layer 5 of opposite conductivity, preferably of p-polarity (referred to as the p-body region), multiple regions of opposite conductivity formed in the p-body region which function as the source region 6, a layer 7 of silicon dioxide, a layer 8 of polysilicon which forms the gate electrode, a layer 9 of deposited oxide (LTO), and a layer 10 of metal.
Susceptibility to breakdown is a phenomenon which limits the power handling capability of a bipolar transistor to below its full potential. In contrast, the power handling capability of a Power MOSFET is a simple function of thermal resistance and operating temperature since the transistor is not vulnerable to a second breakdown mechanism provided that the transistor is operated at or below its breakdown voltage rating B.sub.VDSS and is not subject to overvoltage. Should the transistor be forced into avalanche by a voltage surge, the structure of the transistor permits possible activation of a parasitic bipolar transistor which may then suffer the consequences of second breakdown. In the past this mechanism was typical of failure in circuits where the transistor becomes exposed to overvoltage. To reduce the risk of transistor failure during momentary overloads, improvements have been introduced to the Power MOS design which enable it to dissipate energy while operating in the avalanche condition. The term commonly used to describe this ability is "ruggedness". In devices as illustrated in FIGS. 1 to 6, for example, when such a device is in the off-state or operating in saturation, voltage is supported across the pn-junction. If the transistor is subjected to over-voltage (greater than the avalanche value of the transistor) the peak electric field, located at the pn junction, rises to the critical value at which avalanche multiplication commences. Computer modelling has shown that the maximum electric field occurs on the corner of the p-body. The electron-hole plasma generated by the avalanche process in this region gives rise to a source of electrons which are swept across the drain and a source of holes which flow through the p diffusion or p body regions towards the p+ contact. Clearly, the p region constitutes a resistance which will cause a potential drop beneath the n+ diffusion. If this resistance is too large, the pn-junction may become forward biased for relatively low avalanche currents. Also, if the manufacturing process does not yield a uniform cell structure across the transistor or if defects are present in the silicon, then multiplication may be a local event within the crystal. This would give rise to a high resistance beneath the source n+ region and cause a relatively large potential drop sufficient to forward bias the pn-junction and hence activate the parasitic npn bipolar transistor inherent in the MOSFET structure. Due to the positive temperature coefficient associated with a forward biased pn-junction, current crowding will rapidly ensue with the likely result of a second breakdown and eventual transistor destruction.
In order that a Power MOS transistor may survive transitory excursion into avalanche, it is necessary to manufacture a transistor with uniform cell structure, free from defects throughout the crystal, and within the cell, the resistance beneath the n+ region should be kept to a minimum. In this way a forward biasing potential across the pn-junction is avoided.
The term "ruggedness" when applied to a Power MOS transistor describes the ability of that device to dissipate energy while operating in the avalanche condition. To test the ruggedness of a transistor it is possible to use the method of unclamped inductive-load turn-off using a circuit wherein a pulse is applied to the gate such that the transistor turns on and load current ramps up according to the inductor value, L, and drain supply voltage, V.sub.dd. At the end of the gate pulse, channel current in the Power MOS begins to fall while voltage on the drain terminal rises rapidly in accordance with equation (1). ##EQU1##
The voltage on the drain terminal is clamped by the avalanche voltage of the Power MOS for a duration equal to that necessary for dissipation of all energy stored in the inductor.
The energy stored in the inductor is given by equation (2), where I.sub.p is the peak load current at the point of turn-off of the transistor. EQU W.sub.Dss =0.5LI.sub.p.sup.2 ( 2)
All this energy is dissipated by the Power MOS while the transistor is in avalanche.
Provided the supply rail is kept below 50% of the avalanche voltage equation (2) approximates closely to the total energy dissipation by the transistor during turnoff. However a more exact expression which takes account of additional energy delivered from the power supply is given by equation (3). ##EQU2##
Clearly the energy dissipated is a function of both the inductor value and the load current I.sub.p, the latter being set by the duration of the gate pulse. A 50 .OMEGA. resistor between gate and source is necessary to ensure a fast turn-off such that the transistor is forced into avalanche.
The performance of a non-rugged transistor in response to the avalanche test described above and much of the above technical background has been described in a private communication of Dr. M. J. Humphreys, Philips Components, Hazel Grove, Stockport, Cheshire, U.K. and is published in ELECTRONIQUE DE PUISSANCE, No. 38, pp. 18-25, April 1990. In such testing, it was found that the drain voltage rises to the avalanche value followed by an immediate collapse to approximately 30 V. This voltage is typical of the sustaining voltage during second breakdown of a bipolar transistor. The subsequent collapse to 0 V after 12 microseconds signifies failure of the transistor. One such transistor was only able to dissipate a few micro joules at a very low current in order to avoid a failure of this type.
Thus ruggedness is one of the important performance parameters of VDMOS power devices. As indicated above, in a typical device this parameter is limited by the parasitic resistance of the p-body under the source diffusion, i.e. the Ohmic resistance offered by the device under conductive conditions.
In prior art VDMOS power device structures as illustrated in FIGS. 1 to 6, region 6 is the source, region 11 is the channel, and region 3 is the drain region. The parasitic resistance under the source diffusion determines the ruggedness of the device as measured by the total inductive energy that can be absorbed by the device in the avalanche condition. The device is damaged when the parasitic npn bipolar transistor is turned on by the voltage drop across the resistor R caused by hole current from avalanche breakdown of the p-body/n-drain junction. Therefore, improving the ruggedness of the device can be accomplished by reducing the resistance R such that, higher avalanche hole current is required to turn on the bipolar device. This in turn can be accomplished by providing increased amounts of p-type dopant (boron for example) in the p-body region. However, the same p-body concentration under the gate region determines the threshold voltage of the device and cannot be increased beyond about 2.5 volts, without adversely affecting the device performance. This places an upper limit on the p-body concentration or a lower limit on the parasitic resistance. To surpass this limit, an approach used in the prior art consists of adding another p-type diffusion and a tapered poly gate (shown in FIG. 4). The same constraints on threshold voltage apply here also, thereby again limiting the parasitic resistance value. Furthermore, this approach results in a deeper p-region which degrades the breakdown voltage of the device. Additionally, the tapered polysilicon gate profile needed in this approach makes the process more complex.
Another prior art approach involves the implantation of another p-type layer, defined by a mask with an opening centered between the poly gate edges. (See FIGS. 5 and 6). This implanted layer is then diffused deep vertically and laterally to reduce the parasitic resistance. Again the same limitation on the threshold voltage limits the value of the resistance. Furthermore, the deep p-type diffusion degrades the breakdown voltage. Additionally, this technique needs an extra mask thereby increasing the overall complexity of the manufacturing process.
The prior art methods thus use techniques that involve deep p+ diffusion with a deep junction depth through the use of implantation masks which independently define the heavy boron doping away from the polysilicon gate. This not only expands inner cell dimensions, it also fails to effectively reduce p-body resistance.
In general, prior art devices and techniques may be grouped in several categories: the standard VDMOS without p+ diffusion, non-self aligned p+ diffusion, and self-aligned p+ diffusion techniques and resultant devices.
The standard VDMOS without p+ diffusion is suggested;
Love et al, IEEE Trans. Elect. Dev., ED-31,817 (1984).
Non-self-aligned p+ diffusion techniques and devices are illustrated by the following references:
Goodman et al, U.S. Pat. No. 4,587,713, May 13, 1986
Nakaqawa et al, U.S. Pat. No. 4,680,604, Jul. 14, 1987
Suzuki et al, EPO 336,393 (Europe), Oct. 11, 1989
Chang et al, Insulated Gate Bipolar Transistor (IGBT) With a Trench Gate Structure, IEDM 1987, pp. 674-677;
Temple et al, MCT (MOS Controlled Thyristor) Reliability Investigation, IEDM 1988, pp. 618-621; and
SIPMOS Process, Siemens Component Data Book, 1987/1988.
In all of such p+ diffusion techniques and devices as described in these references, the low resistance p+ diffusion is formed using a photoresist mask and is therefore a non-self-aligned method. When the fabrication method is not self-aligned, cell dimensions are increased thereby increasing the effective cost of the device. Additionally although such methods improve the ruggedness of the device, they cannot be used to produce the high density device that forms the subject of this investigation. This type of non-self-aligned method and device is referred to below as the conventional method and device.
Prior art self-aligned p+ diffusion techniques and devices are illustrated by the following references: Goodman et al, U.S. Pat. No. 4,587,713, May 13, 1986
Contiero et al, U.S. Pat. No. 4,774,198, Sep. 27, 1988
Temple et al, U.S. Pat. No. 4,809,047, Feb. 28, 1989
Yasukazu, Abstract of JP application 62-196917 (Japan), Feb. 10, 1989.
In the techniques and devices represented by such references, although the low resistant p+ diffusion region is formed by a self-aligning technique, the devices are still deficient. For example, in the Contriero and Temple et al patents, p+ implantation is done using either oxide spacers at the polysilicon step or oxide grown around the polysilicon. Similarly, in Yasukazu, the implantation mask is a deposited oxide having 3.mu. eaves from the polysilicon gate. In each such procedure, the p+ diffusion cannot be formed close enough to the channel to effectively reduce resistance in the p-body. Furthermore, the additional 3.mu. ring or rectangular dimension added in such techniques as illustrated by Yasukazu expands cell size by the same amount making it large. The oxide spacers or surrounding oxides of the Contiero et al and Temple et al devices generate similar results.